This invention relates to a manufacturing method of semiconductor devices and more particularly to MOS-type devices which have extraordinarily small dimensions.
During the past several years there has been a continuing trend toward the development of semiconductor devices having extraordinarily small dimensions of the order of 1 micron or less to increase the packing density of devices on an integrated circuit chip. Particularly in the area of MOS memories, gate widths and associated interconnect dimensions continue to be scaled down to increase not only the circuit density on the chip but also to improve the circuit performance (by increased operational speeds, etc.). As these dimensions continue to decrease, several problems, which significantly reduce yields and thereby offset the cost savings achieved by higher packing density, become manifest. One of these problems is hot-carrier (i.e. hot-electron or hot-hole) injection from the channel region into the gate oxide due to very high electric field intensities in a narrow channel region adjacent the drain. Such charge injection into the gate oxide and the subsequent trapping of these charges therein will cause device instabilities such as threshold-voltage shift and transconductance degradation.
Another problem encountered in manufacturing small geometry MOS devices relates to electrical shorts between interconnecting conductors such as the electrical conductor contacting the self-aligned gate, source and drain. To elaborate on this point, in the fabrication of silicon gate MOS devices after forming the polysilicon gate structure and the source-drain regions in correspondence with the gate structure, a metal such as tungsten is selectively deposited over the polysilicon gate and the source-drain regions of the silicon substrate to provide low resistance conductor lines. However, the metal deposited in this manner invariably forms a shroud around the polysilicon gate which tends to create an electrical short with the metal deposited over the adjacent source-drain regions. A similar shorting problem exists between adjacent closely-spaced polysilicon interconnect lines.
To alleviate the first of the above problems, a lightly doped drain-source (LDD) structure has been proposed. In a LDD n-MOSFET structure, for example, very shallow, self-aligned lightly doped n.sup.- regions are introduced between the channel and the heavily doped, less shallow n.sup.+ source-drain diffusions. This structure increases breakdown voltage and reduces impact ionization (and thus hot-electron emission) by spreading the high electric field at the drain pinchoff region into the n.sup.- region.
One method of fabricating LDD structures is by using the sidewall spacer approach in conjunction with the state-of-the-art etching techniques such as anisotropic (and selective) reactive ion etching (RIE). Reference is now made to the publication entitled "Fabrication of High Performance LDD FET's With Oxide Sidewall-Spacer Technology" by P. J. Tsang et al. and published in IEEE Transactions on Electron Devices, Vol. ED-29, No. 4, April, 1982, pp. 590-596, which teaches a method of forming the LDD n-MOS FET. In this method, after forming the polysilicon gate structure consisting of the gate oxide, the polysilicon gate and an SiO.sub.2 etch mask, n-type ion (e.g., phosphorus) implantation is accomplished to form the lightly-doped source-drain regions. A layer of CVD SiO.sub.2 of a desired thickness is then conformally deposited and, using directional vertical RIE, the planar portion of the CVD oxide is removed. As a result of this etch, an oxide sidewall spacer is left abutting the polysilicon gate structure where the deposited oxide is thicker in the vertical direction. Following the formation of the sidewall spacer, arsenic ion-implantation is used to form the n.sup.+ regions of source and drain.
In the Tsang et al. process, since the oxide mask over the polysilicon gate is not removed during the RIE, it would appear that a subsequent etching step to remove the oxide mask will considerably thin down the oxide sidewall spacer. Consequently, upon forming the metal over the polysilicon and the substrate regions corresponding to the source and drain, by selective deposition, for example, the device is prone to shorting problems discussed previously.
Reference is now made to U.S. Pat. No. 4,330,931, issued on May 25, 1982, to Liu which discloses a process for forming a self-aligned silicon gate n-MOSFET having n.sup.- source-drain extensions. In this process after forming the polysilicon gate having a nitride overhang mask, arsenic ions are implanted to form the n.sup.+ source and drain. During this implant step, lightly doped source-drain extensions are also formed due to blocking of some ions by the nitride overhangs. The structure is then subjected to a high temperature (920 degrees C.) oxidation step to grow a 1000 Angstroms thick oxide over the sides of the polysilicon gate and the substrate corresponding to the source-drain regions. The oxide thus formed over the n.sup.+ source-drain regions is then damaged by argon ion bombardment. During this oxide damaging step, the oxide over the n.sup.- source-drain regions and the sidewalls of the gate is protected by the nitride mask. The damaged oxide and the nitride mask are then removed and a tungsten layer is selectively deposited over the exposed n.sup.+ source-drain regions and the gate.
The Liu process requires an oxide damaging step which is not only an extra process step but also requires very careful control lest the source-drain areas may also be damaged. Both of these requirements are particularly disadvantageous from a high volume manufacturing standpoint. Another disadvantage is that this process requires forming a nitride overhang mask atop the polysilicon by undercutting the polysilicon. This is a critical process step and is very difficult to control. Further, any variation in undercutting the polysilicon may cause possible damage to the sidewall oxide during argon ion bombardment. Yet another disadvantage of the Liu process is that this process appears to be limited to forming a very thin (1000 Angstroms thick) polysilicon gate sidewall oxide. Consequently, upon selective deposition of tungsten over the polysilicon gate and the source-drain areas, adjacent tungsten strips may short each other out due to tungsten spiking.
It is an object of the present invention to prevent the aforementioned shorting between closely-spaced adjacent metal conducting lines.
It is another object of this invention to provide a controllable and reproducible manufacturing process of forming a short channel MOS device having a graded doping profile source-drain regions for minimizing hot-carrier effects.